Archives May 2016 - 3D InCites

“How Do You Create The Future?” Through Innovations in Heterogeneous Integration and SiP

“How Do You Create The Future?” Through Innovations in Heterogeneous Integration and SiP

MEPTEC Luncheons returned big to The Bay Area on Wednesday, May 25, 2016, with a new venue (SEMI HQ), a new joining of forces (IMAPS-MEPTEC-SEMI), a great turn-out (fully committed, capacity-wise, as they say in the restaurant biz), and an inspiring talk by Bill Chen, ASE Fellow and Senior Technical Advisor, ASE Group. As devoted readers of 3D InCites / 3D+ know, we started this blog in 2014 to fo... »

Meet Me at ECTC 2016 in Las Vegas

Meet Me at ECTC 2016 in Las Vegas

With the industry-wide shift in focus from furthering Moore’s Law to the realization that 3D integration and advanced packaging technologies are the shining stars of the next generation of electronics, the 66th Annual IEEE Electronic Components Technology Conference, which takes place May 31-June 3, 2016, at the Cosmopolitan of Las Vegas, promises to be one of the best ever. The agenda boasts 39... »

IPSO Challenge Update: The Smart Rock Bolt Success Story

IPSO Challenge Update: The Smart Rock Bolt Success Story

Six months ago, I interviewed Jens Eliasson, associate professor at Luleå University of Technology (LTU), and co-developer of the Smart Rock Bolt, a vibration-sensor-based device used for instrumenting tunnels in mines to detect potential catastrophic collapses. He had just accepted the IPSO Challenge grand prize on behalf of his team. That story is here. I caught up with him after IoT World for... »

Convergence on the “Big Five”: Focus on WLCSP

Convergence on the “Big Five”: Focus on WLCSP

Part two of a five-part series. How did we determine which technologies are “the Big Five,” for semiconductor packaging? Essentially, we identified the five key platforms that we believe will be leveraged across a multitude of applications and markets now and in the future. The selected platforms are low-cost flip chip, wafer-level chip scale packaging (WLCSP), micro-electromechanical systems... »

EV Group Receives Multiple Orders for GEMINI® FB XT Fusion Wafer Bonder for 3D Chip Stacking Production Applications

EV Group Receives Multiple Orders for GEMINI® FB XT Fusion Wafer Bonder for 3D Chip Stacking Production Applications

EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has received multiple orders for its GEMINI® FB XT automated fusion wafer bonders from multiple leading device manufacturers. The GEMINI FB XT offers industry leading wafer-to-wafer alignment accuracy, customizable pre- and post-processing c... »

ASMC 2016, the Return of MEPTEC Luncheons, and Your May Calendar

ASMC 2016, the Return of MEPTEC Luncheons, and Your May Calendar

The Saratoga Springs, NY, horse racing season starts in late July, following a racing tradition that dates to the 1860s. That’s a pretty long run indeed, and it’s one of the things, along with the healing spring waters, successful Revolutionary War battle history, and “summering” by well-to-do Boston and New York families, that gives Saratoga its charm. At first glance, Saratoga might be a... »

Challenges and Solutions for EDA of 3D Chip Stacks

Challenges and Solutions for EDA of 3D Chip Stacks

It is often claimed that 3D chip stacks offer the potential to meet current and future requirements of digital circuits, such as for performance, functionality, and power consumption. Specifically, both design paradigms “More Moore” and “More than Moore” will benefit from 3D chip stacking (and new technologies and materials). 3D stacking enables notably reduced interconnect... »

Amkor and Cadence to Develop PADK for Amkor’s SLIM and SWIFT Packaging Technologies

Amkor and Cadence to Develop PADK for Amkor’s SLIM and SWIFT Packaging Technologies

TEMPE, Ariz., May 2, 2016 — Amkor Technology, Inc. (NASDAQ: AMKR), a leading outsourced semiconductor packaging and test service provider, today announced the expansion of its collaboration with Cadence Design Systems, Inc. (NASDAQ: CDNS) to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor’s SLIM™ and SWIFT™ advanced... »

Transforming Today’s Semiconductor Industry Challenges into Tomorrow’s Opportunities

Transforming Today’s Semiconductor Industry Challenges into Tomorrow’s Opportunities

My wife, born and raised in Hong Kong, tells me that the Chinese language uses the same word for challenge and opportunity. What can we, in the 200-year-old  US of A, learn from the 4000 years old Chinese culture? The Chinese have a point! Based on my personal experience, I have to say that every challenge I faced so far, opened a door to a new opportunity, making my life better and more interest... »

Cypress Subsidiary Deca Technologies to Receive $60 Million Investment from ASE

Cypress Subsidiary Deca Technologies to Receive $60 Million Investment from ASE

SAN JOSE, Calif.,- Advanced Semiconductor Engineering, Inc. (TAIEX: 2311, NYSE: ASX and Deca Technologies, a subsidiary of Cypress Semiconductor Corp. (NASDAQ: CY), today announced the signing of an agreement whereby ASE will invest $60 million in Deca and will license Deca’s M-Series™ Fan-out Wafer-Level Packaging (FOWLP) technologies and processes. As part of the agreement, ASE and Deca will... »