Archives February 2015 - 3D InCites

Xilinx Ultrascale+: 3D on Steroids

Xilinx Ultrascale+: 3D on Steroids

Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family of 3D integration technology possibilities, we’ve been careful to define them separately on 3D InCites. Some people have wondered if one will displace the other, or if these technologies would delay the adoption of 3D stacked ICs using TSVs. I maintain that these technologies h... »

RIP ITRS V1.0: 1992-2015

RIP ITRS V1.0: 1992-2015

Prior to 1992, the high technology industry was ‘immature’. Each supply chain vendor (equipment, materials) would accumulate input from their customers that defined product roadmaps. Vendors cared little about accepting or supplying work-in-progress (WIP) to other vendors’ products. But it became obvious to many that unless they were coordinated, sales potential would be limited. A coordina... »

Heterogeneous Integration Spoor In MEMS and Sensor Start-ups

Heterogeneous Integration Spoor In MEMS and Sensor Start-ups

The distinguished journalist Peter Clarke, writing in EETimes on 02 January 2015, identified what he called the “15-in-15: Analog, MEMS and sensor start-ups to watch in 2015.” What better place to shine the heterogeneous integration spotlight than here, I thought, when I read the piece in January – as Peter wrote, “The blossoming of the [Analog, MEMS, Sensor] sector may be to do with the g... »

Can Path Finding be used in the Production Environment?

Can Path Finding be used in the Production Environment?

In previous posts, I have discussed various scenarios when Path Finding can be used. All were focused on the early design process: implementation guidelines, robust design and process centering. But what if you have a design in production and ‘something’ happens; like a process is no longer available; a component must be replaced by another, yields become erratic, etc. Is there a role for Path... »

The X-ray Metrology of TSVs and Wafer Bumps

The X-ray Metrology of TSVs and Wafer Bumps

Being able to look inside an object without opening it up or destroying it, and separating the different features within that would otherwise overlap each other when seen in a standard 2D X-ray image, are the same for the needs of electronics inspection on wafers and on printed circuit boards, as they are in the medical sphere. If there is a problem on a wafer (or a person!) ideally we want to ana... »

DesignCon 2015: Blasting Through Walls with Holistic Planning

DesignCon 2015: Blasting Through Walls with Holistic Planning

DesignCon’s 2015‘s tag-line “where the chip meets the board”, was a very appropriate message, and summarized in a few words a major trend in our semiconductor- and electronic systems industry: The increasing need for holistic planning as well as modeling of building blocks, not only for better up- and down-stream communication between design steps, but also for closer cooperation betwe... »

Riding Out on a Horse and in on a Goat: 3D IC Predictions for MEMS

Riding Out on a Horse and in on a Goat: 3D IC Predictions for MEMS

The Lunar New Year is soon upon us, and we will be celebrating the Year of the Goat with firecrackers, red packets (I hope!), and the evening parade in San Francisco on 07 March 2015. The goat is a sturdy animal whose praises are often undersung. Undersung – that sounds a little bit like the MEMS Industry, which, as I wrote in 2014, is sometimes looked upon as being the poor cousin of the se... »

ESD in 3D IC Packages

ESD in 3D IC Packages

For single die packages, electrostatic discharge (ESD) is well understood, and precautions are taken to minimize the possibility of charge build-up and ESD strikes. In single die designs, Input-Output (I/O) cells contain robust ESD protection circuitry. Additionally, ESD precautions are considered throughout the design, development, fabrication, and assembly/test of devices. As we move toward more... »

Advanced Packaging Challenges and Opportunities for 2015

Advanced Packaging Challenges and Opportunities for 2015

Our industry is seeing greater diversification in manufacturing processes than it has since its earliest days. In the front-end numerous new materials, architectures, and processes are under development to enable the continuing march toward smaller device sizes. In the back-end, and many places in between, advanced packaging processes and 3D integration are adapting processes from the front-end, v... »

Silicon Photonics and 2.5D Interposer Design

Silicon Photonics and 2.5D Interposer Design

Historically, we all took Moore’s Law for granted. With each new node, we could expect to see faster-performing devices, smaller design footprints and, ultimately, lower design costs. Nowadays these benefits are not clearly achievable for all designers. At the latest advanced technology nodes, we may be able to see faster devices through the miracles of finFET technologies, but do we really get ... »

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