Archives December 2014 - 3D InCites

Path Finding Series Part 2: What if I do not have a robust design?

Path Finding Series Part 2: What if I do not have a robust design?

In previous posts, I discussed Robust Design analysis as orthogonal Path Finding. This analysis is performed while the design implementation is held constant but with varying manufacturing process parameters. This will determine how sensitive a design is within the process(es) it will be manufactured. The previous post highlighted the negative consequences if a design is released to manufacturing ... »

3D ASIP 2014: All Aboard the 3D IC Train!

3D ASIP 2014: All Aboard the 3D IC Train!

Like the previous 10 years, RTI International held the 11th 3D-IC focused conference in early December. Instead of the usual two and a half days, this year it spanned 3 days, because it also offered a 4-hour session about 3D design challenges and solutions available from foundries, EDA and IP vendors, a power-user’s 3D views, as well as a low-power design tutorial presented by Si2’s Jerry Fren... »

3D ASIP 2014 Sparks Mixed Reactions from the Media

3D ASIP 2014 Sparks Mixed Reactions from the Media

Isn’t it interesting how different people attending the same event can come away with different perspectives? I attended last week’s 3D Architectures for Semiconductor Integration and Packaging (3D ASIP 2014), and came away feeling euphoric about what the 3D industry has achieved since last 3D ASIP, and all its promise for the future. After following the technology progress and believing in i... »

Happy Holidays from the 3D InCites Family to Yours!

Happy Holidays from the 3D InCites Family to Yours!

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Live Long and Prosper in an IoT World enabled by 3D ICs

Live Long and Prosper in an IoT World enabled by 3D ICs

Wait – was that a Klingon I just saw walking through the lobby? Are those two people wearing Star Trek uniforms? By pure coincidence, this year’s 3D Architectures for Semiconductor Integration and Packaging Conference (ASIP 2014), which took place in Burlingame, CA, December 10-12, 2014, overlapped with the 2014 Star Trek Convention. After several days of listening to talks about a future enab... »

Invitation to Participate in Si2 Survey

Invitation to Participate in Si2 Survey

Dear Semiconductor / EDA expert, In my role as business development consultant, I, Herb Reiter, am getting involved in many new technologies, interesting business opportunities and meeting influential people – like 3D InCites’ Francoise von Trapp. At last week’s 3D ASIP Conference in California, Francoise offered to encourage you to answer a brief survey that will help Si2 and me, in my role... »

3D ASIP Pre-Conference Symposium brings together Design and Process for 3D ICs

3D ASIP Pre-Conference Symposium brings together Design and Process for 3D ICs

Despite efforts to leverage the one hour time difference from Phoenix to San Francisco to my advantage, I arrived on the scene at the 2014 3D ASIP Conference to find the morning Pre-conference Symposium on (Interposer) and 3D Design Tools and Flows already well underway. My absence did not go un-noticed by the first presenter, Bill Martin, E-System Design, or by the session organizer and fellow 3D... »

Path Finding Series Part 1: NOT a One-trick Pony

Path Finding Series Part 1: NOT a One-trick Pony

In previous posts, I discussed a classical Path Finding methodology.¹ Classical is when various design variables are arranged in different configurations while holding Process Variables (variation) constant. Examples would be: vary the RDL pitches, vary the size of balls or pillars used, vary the length/diameter of wire bonds, etc. This allows Path Finding to identify the solutions that meet requ... »

Samsung’s 3D V-NAND Flash Product: Ceaselessly Marching

Samsung’s 3D V-NAND Flash Product: Ceaselessly Marching

What a feast of information Techinsights has given us on Samsung’s 32-layer 3D V-NAND product! By adding dimensions to the cross sections and including the orthogonal direction, we can now add to what we discerned last time and see how Samsung has built this engineering wonder. As a reminder, Figure 1 shows what I thought was a reasonable guess based on Chipworks analysis. Notice that I couldn... »

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

We’ve heard it expressed many times whenever there’s a new interconnect technology vying for adoption: manufacturers will select the best performing option at the lowest cost to do the job. However, as performance requirements reach previously un-anticipated levels, pitch requirements become tighter, and density requirements become higher, the job of the packaging engineer to provide increased... »

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