Archives September 2014 - 3D InCites

Book Review: Vertical 3D Memory Technologies

Book Review: Vertical 3D Memory Technologies

“From so simple a beginning endless forms most beautiful and most wonderful have been, and are being, evolved.” ~ Charles Darwin Charles Darwin was obviously not thinking of 3D semiconductor memories when he said this but the thought is appropriate. With the recent introduction of the first monolithic 3D Flash memory, the time is ripe to describe how the industry came to this point and what ot... »

Courtesy of Cadence - 3D By Design

3D By Design: A Blog By and For the 3D Design Community

Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D integration technologies as a solution to dealing with the increasing complexity of SoC designs. The post was inspired by my attendance at the Design and Test Europe (DATE 2014) conference, where I moderated a session on system on chip (SoC) design complexity, and ... »

Addressing 3D Integration Challenges: Designing Materials for a Complex Landscape

Addressing 3D Integration Challenges: Designing Materials for a Complex Landscape

3D integration has created a complex landscape of many different package architectures and integration approaches that have diverse materials needs and uncertain insertion timing. The multitude of processes required do not fit neatly into the established pigeonholes of front-end and back-end. Processes such as through silicon via (TSV) fabrication require wafer processing equipment, materials and ... »

TechSearch International 3D IC Gap Analysis Details Market Growth for 3D ICs and 2.5D Interposers

TechSearch International 3D IC Gap Analysis Details Market Growth for 3D ICs and 2.5D Interposers

Major DRAM makers Micron, SK Hynix, and Samsung have announced versions of stacked memory with through silicon vias (TSVs) for high-performance applications. Some CMOS image sensors are also in production with die stacking and TSVs. The remaining question is what is holding back the expansion of 3D IC in other applications? TechSearch International’s 3D IC Gap Analysis: Remaining Issues, Solutio... »

Kulicke & Soffa Stack the Dice for 2.5D and 3D IC Assembly

Kulicke & Soffa Stack the Dice for 2.5D and 3D IC Assembly

It’s been a long time coming, but Kulicke & Soffa has seen the writing on the wall, and it reads: “2.5D and 3D IC assembly is a hot market.” Why else would the wire-bond giant invest in developing a thermocompression chip-to-substrate (C2S) bonder for high-volume 2.5D and 3D IC die stacking processes? The company first dipped its toes in the die bonding market when it acquired Alphas... »

What are the Major Trends Shaping the Future of the IC Industry?

What are the Major Trends Shaping the Future of the IC Industry?

Last week, I caught IC Insights’ Bill McClean’s talk at the IMAPS Arizona luncheon. In addition to predicting a steady growth trend for the semiconductor industry that will reach double digits by 2016, followed by a cyclical downturn to -1%in 2017, McClean also discussed some major trends he expects will shape the future of the IC industry worldwide. While worldwide electronic systems prod... »

3D IC Notes from SEMICON Taiwan 2014

3D IC Notes from SEMICON Taiwan 2014

I attended the 3D IC Technology Forum at SEMICON Taiwan 2014, where many of the discussions focused on the latest memory announcements in 3D ICs from Micron, SK Hynix, Samsung, and Tezzaron. While the world still waits for the introduction of a Wide I/O mobile DRAM and logic part, memory is clearly moving into production. The focus of Taiwanese OSATs in the 2.5D space, such as SPIL and ASE, is to ... »

The Future of Image Sensors is Chip Stacking

The Future of Image Sensors is Chip Stacking

CMOS image sensors (CIS) have often been heralded as the first 3D devices in volume manufacturing. However, this is not really the case. Shellcase MVP, the first generation of CIS that used through silicon vias (TSVs) to form interconnects was still a 2D device. (Remember, TSV is not always synonymous with 3D). Chip stacking only came about with the advent of backside illuminated (BSI) CIS and ... »

The Intel Developer Forum 2014

The Intel Developer Forum 2014

This week I had the privilege to attend my first Intel Developer Forum (IDF). Like many of us, I have become more energy-conscious, so took the train to get there and back. On my way back I didn’t have to concentrate on the traffic around me and had time to think about what I learned from Intel’s keynotes and Mega-sessions on the first day. For many years, Intel has been the world’s largest... »

Fermilab Implements Ziptronix’s DBI Hybrid Bonding  in High-End 3D Image Sensors

Fermilab Implements Ziptronix’s DBI Hybrid Bonding in High-End 3D Image Sensors

Ziptronix Inc. today announced that its Direct Bond Interconnect (DBI) hybrid bonding has been implemented by Fermi National Accelerator Laboratory (Fermilab) to improve the performance of high-end 3D sensor arrays, which are used for particle detection in large-scale particle physics and x-ray imaging experiments. This is an example of three-layer DBI hybrid bonding in a 3D imaging chip, using D... »

Page 1 of 212