Archives August 2014 - 3D InCites

Will 2.5D and 3D Stacking Save the Semiconductor Industry?

Will 2.5D and 3D Stacking Save the Semiconductor Industry?

Year’s ago, when I was managing editor of Advanced Packaging Magazine, each January issue featured an industry forecast cover story. For several years in a row, that issue predicted advanced packaging would be the key to improved performance at lower power and lower cost. January of 2007, we declared “Packaging Saves the World!” and in January of 2008, the cover story was “Packaging Drive... »

Glass Substrates for Advanced Packaging

Glass Substrates for Advanced Packaging

Glass has many properties that make it an ideal substrate for interposers such as: ultra-high resistivity and low electrical loss, low dielectric constant, and adjustable coefficient of thermal expansion (CTE). Leveraging glass-forming processes such as Corning’s fusion forming process provides roughness < 0.5nm rms, and flat substrates with good stiffness. These properties provide opportunit... »

Highlights from HotChips 2014: 21 HBM Design-ins Ongoing!

Highlights from HotChips 2014: 21 HBM Design-ins Ongoing!

Last week, HotChips 2014 (aka HC26) was held at the Flint Center within the De Anza College in Cupertino, California. As in many previous years, I attended both the Sunday tutorial and the main conference on Monday and Tuesday. As usual, there were great keynotes and lots of interesting technology news. The tutorial always focuses on an important technology or market trend. This year was no e... »

Lithography Process Innovations Part 2: Improving Thermo-mechanical Reliability of TSV Interconnects

Lithography Process Innovations Part 2: Improving Thermo-mechanical Reliability of TSV Interconnects

In Part 1 of this article series, we noted that despite the potential benefits associated with 3D and interposer-based 2.5D designs, the incorporation of TSVs poses significant challenges to the performance and reliability of 3D wafer level packages (3D WLP). Among these is the generation of TSV stress in 2.5D/3D packaging – both thermal-induced stress resulting from the coefficient of thermal e... »

Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress

Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress

As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package architectures has become key to enable the integration of greater amounts of chip functionality in smaller form factors. This need for form factor reduction, together with smaller process geometries and higher-count I/O on int... »

Are Chip Architects Finally Climbing on the 2.5D and 3D Bandwagon?

Are Chip Architects Finally Climbing on the 2.5D and 3D Bandwagon?

Ever since SEMICON West 2014, I’ve been seeing a lot of coverage of the 2.5D and 3D adoption question on Semiconductor Engineering, an industry content platform that covers the spectrum of semiconductor topics, and occasionally covers 2.5D and 3D, providing the perspective of chip architects, engineers, end users, industry organizations and standards bodies. What I find most interesting in these... »

Samsung’s 3D V-NAND Flash Product – The Spires of El Dorado?

Samsung’s 3D V-NAND Flash Product – The Spires of El Dorado?

Finally! After a year’s worth of guesswork, Samsung’s 3D V-NAND Flash cell has been revealed. Thanks to the expertise of Chipworks we can see how the memory array looks in the 86 Gbit 32-layer 2nd generation V-NAND. Figure 1 shows Chipworks’ beautiful cross section. My intention here is to explain the structure, compare it with what I have written about before and, of course, give my opini... »

Rudolph Receives Volume Purchase Order from Major Taiwan OSAT for 2D/3D Inspection Systems

Rudolph Receives Volume Purchase Order from Major Taiwan OSAT for 2D/3D Inspection Systems

Flanders, New Jersey (August 11, 2014)—Rudolph Technologies, Inc. announced today that it has received a large order from one of Taiwan’s providers of independent semiconductor manufacturing services in assembly and test (OSAT) for 2D/3D inspection systems. The order includes: multiple NSX® systems for two-dimensional (2D) macro defect inspection, the Wafer Scanner™ Inspection Series for th... »

IWLPC 2014 To Feature 3D InCites Panel: System-level Advantages of 3D Integration

IWLPC 2014 To Feature 3D InCites Panel: System-level Advantages of 3D Integration

For the first time this year, 3D InCites is sponsoring a panel discussion at  IWLPC on the topic of System-level Advantages of 3D Integration. For years the industry has discussed and debated 3D integration technologies, discussing the market drivers, technology challenges, supply chain issues, and above all, the cost. As the roadmaps continued to be pushed out, manufacturers, suppliers, and R&am... »

Low-Temp, Ultra-Fine-Pitch Cu Interconnections for Manufacturable, Solder-free Assembly

Low-Temp, Ultra-Fine-Pitch Cu Interconnections for Manufacturable, Solder-free Assembly

A novel copper interconnection technology is being pioneered by Georgia Tech’s Packaging Research Center (GT-PRC) to achieve manufacturable solder-free assembly at low temperatures. By interfacing engineering and process design, the Cu interconnections are shown to meet both thermal cycling and ultra-high current-handling needs. This technology is now being applied to mobile and high-perfor... »

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