Archives March 2014 - Page 2 of 2 - 3D InCites

Is the Road to 3D ICs Paved with 3D SOC?

Is the Road to 3D ICs Paved with 3D SOC?

Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its name is 3D SoC (aka: 3D system on a chip, or 3D system partitioning, or mixed node integration – take your pick). Whatever the moniker, it looks like THIS is going to be the one to remember most, as its likely to finally provide the technology/cost advantage that makes 3D ICs worth ... »

Interconnectology Revisited: Pizza Anyone?

Interconnectology Revisited: Pizza Anyone?

Interconnectology returned as a topic of discussion to the 2014 BiTS Workshop through a keynote discussion delivered by Invensas’ president, Simon McElrea. His talk, aptly titled “Interconnectology: the Road to 3D” addressed the need not only for innovations in interconnect technology that focus less on silicon innovation and more on advanced packaging; but equally about the intercon... »

EV Group Boosts 2.5D and 3D-IC/TSV Performance with New Nanospray Application

EV Group Boosts 2.5D and 3D-IC/TSV Performance with New Nanospray Application

ST. FLORIAN, Austria, March 12, 2014 — EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that its patented NanoSpray conformal coating technology is now available on its newly introduced EVG150XT resist coating and developing system for high-volume manufacturing (HVM) semiconductor applications. ... »

Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »

Akrion Systems Commences Joint Development Programs for 3D Integration Processes with Leading Research Organizations

Akrion Systems Commences Joint Development Programs for 3D Integration Processes with Leading Research Organizations

Allentown, Pa., March 5, 2014 – Akrion Systems recently engaged in two new Joint Development Programs (JDPs) with leading-edge semiconductor research organizations, both located in Europe. The two programs are focused on wet processing areas in the 3D integration of semiconductor devices. The work in both partnerships will focus on improving yields and reducing costs for critical process steps ... »

SUSS MicroTec launches DSC300 Gen2: Next Generation Projection Scanner for Advanced Packaging

SUSS MicroTec launches DSC300 Gen2: Next Generation Projection Scanner for Advanced Packaging

Garching, March 4, 2014 – SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has launched the DSC300 Gen2 projection scanner today. SUSS MicroTec’s DSC300 platform for wafer sizes up to 300mm is based on the projection lithography technology developed by SUSS MicroTec Photonic Systems Inc. (formerly Tamarack Scientific). The ... »

Magic Chip-powered SuperPoP offers Near-term Alternative to TSVs

Magic Chip-powered SuperPoP offers Near-term Alternative to TSVs

When I saw that Dev Gupta, Ph.D, of Advanced Packaging & Systems Technology Laboratories, LLC (APSTL) was presenting at the IMAPS Arizona Chapter luncheon last week, there was no questioning my attendance. Dr. Gupta has been an active participant on 3D InCites, offering regular commentary on posts, so I was particularly eager to hear and report on what he had to say on his chosen topic of the ... »

Dynaloy™ Researchers to Detail One-Step Cleaning Process for TSVs

Dynaloy™ Researchers to Detail One-Step Cleaning Process for TSVs

INDIANAPOLIS, Ind., February 24, 2014 – A team of researchers from Dynaloy and Solid State Equipment Corporation (SSEC) have developed a robust, one-step cleaning process for TSVs for the removal of post etch residue. Kim Pollard, Technology Manager at Dynaloy, will discuss this new cleaning process and chemistry at the Device Packaging Conference for the International Microelectronics Assembly ... »

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