Archives October 2013 - 3D InCites

NANIUM Extends eWLB to Achieve Higher Reliability

NANIUM Extends eWLB to Achieve Higher Reliability

NANIUM S.A. has introduced an improved dielectric material and process solution for its fan-out wafer-level packaging (FOWLP) technology, embedded wafer-level ball grid array (eWLB). These improvements increase eWLB’s reliability, thereby extending the existing technology platform into more demanding markets and applications including medical devices, aerospace and automotive, among others. ... »

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feat... »

Triton Microtechnologies Receives Funding to Ramp Glass Interposer Manufacturing for 3D and 2.5D Semiconductor Packaging

Triton Microtechnologies Receives Funding to Ramp Glass Interposer Manufacturing for 3D and 2.5D Semiconductor Packaging

Start-up Triton Microtechnologies, a designer and manufacturer of ultra-thin glass interposer technology that enables advanced semiconductor-packaging solutions, has met six-month production milestones that have triggered an additional $3.2M in funding from parent companies Asahi Glass Co., Ltd. (AGC) of Tokyo and nMode Solutions Inc. in Oro Valley, Arizona. Triton will invest the capital to furth... »

Courtesy of Governor Cuomo's press office

Nano Utica gets $1.5B Infusion; Probably Good Die Revisited; Developments in Monolithic 3D

Word on the street is, New York will soon be known as Nano York, with all the money the state is pouring into nanotechnology research and development. The most recent announcement by Governor Cuomo is a $1.5 Billion Public-Private investment intended to turn the Mohawk Valley (Utica) into the next major hub for nanotechnology research. A consortium of global technology companies headquartered at t... »

IMAPS International 2013

IMAPS International 2013 3D Technology Highlights

Approximately 880 people registered for IMAPS International 2013, and yes the fiasco in Washington even affected IMAPS – there were last minute cancellations from people who work directly or indirectly for the government. But I was there, and here are the highlights: Qualcomm : Vidhya Ramachandran presented data on a prototype 3D memory on logic package. The paper was co-authored with TSMC. Yup,... »

courtesy of NORDSON Asymtek

Is it Time for Fluxless Processes for 3D Packaging?

A 3D InCites reader recently inquired whether cost drivers and fine-pitch requirements in 3D applications are moving manufacturers away from flux towards fluxless processes in the bumping steps for both bump formation and assembly.To answer this question, 3D InCites turned to the materials and equipment experts, speaking with Jeff Calvert, Global R&D Director, Advanced Packaging Technologies a... »

The Small Scale Systems Integration and Packaging (S³IP) Center

3D ICs for High Performance Systems

A recent IEEC and IEEE CPMT workshop held on October 16, 2013 at Binghamton University in New York examined the status of 2.5D and 3D ICs for high performance systems. There is no question that 3D ICs with through silicon vias (TSV) remain driven by concerns over astronomical lithography cost at future silicon technology nodes, requirements for high bandwidth between the memory and processor, lat... »

Internet of Things

A Breakfast of Cu Pillars, Wafer-level Packaging the Internet of Things, and more

I took a detour to work on Friday (Oct 18, 2013), stopping in at Freescale Semiconductor (Tempe AZ) to attend the Arizona SEMI Breakfast Forum. The topic was right up my alley: (which is why I went, of course!) “New Advanced Packaging Insights on Technology and Applications“. Featured speakers included Garrett Oakes, EV Group, who focused on copper (Cu) pillars from “lab to fab”; Semic... »


3D NAND Flash – Towering Spires or Costly Canyons?

The transition to 3D NAND Flash seems to be imminent with projections of it being half the total NAND Flash market by 2016. That means tens of billions of dollars within 3 years. V-NAND is Samsung’s version. Their first publication describing this architecture was released in 2009 and was called “TCAT” or “Terabit Cell Array Transistor”. Toshiba too has been working o... »

Catching Up with Dongkai Shangguan about NCAP China

Catching Up with Dongkai Shangguan about NCAP China

If you have an ear out for the new in the world of 3D IC technology as I do, then you might have caught one of the more interesting, and one of the freshest, voices in the field among the panelists speaking at the recent MEPTEC Semiconductor Roadmap Symposium in Santa Clara, CA. That new voice belongs to Dr. Dongkai Shangguan, who is CEO of the National Center for Advanced Packaging, recently (CY... »

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