Last week, I heard from the North American delegation of the Jisso International Council (JIC), reporting on the recently concluded annual meeting at the Minatec facilities in Grenoble France, which this year was focused on 3D terminology. Collectively, they contributed the following guest post:

The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France, at which the third dimension was a key topic. JIC’s interest in 3D is predicated on their ongoing efforts to harmonize standardization and industry terminology for electronic interconnections. 3D interconnections are blurring the once well-defined and bright lines that separated the various hierarchical elements of the electronics universe. As a result, the council is now looking for ways to help the broader industry communicate more effectively as these nascent technologies begin to take hold and grow.

There were several excellent and informative presentations made by council members in an effort to help identify and resolve some of the many challenges that accompany the development and growth of this new area of high interest to the electronics design and manufacturing community. In the first part of the JIC’s 3D session, Eric Beyne, IMEC (Belgium), Nicolas Sillon, CEA- Léti (France) and Juergen Wolf, Fraunhofer Institute (Germany) provided a comprehensive review of the economical considerations of the various TSV technologies that are increasingly popular.

3D technology, it was concluded, is essentially a collection of stacked chip versions using both “vias-first” and “vias-last” production methods. Related technologies not only allow for the stacking or layering of interconnect routing layers, as has long been the design tradition, but now also allow the stacking of actual active component layers to provide a “More than Moore” total integration solution. This is perhaps the most distinctive feature of 3D integration, as it allows for the realization of electronic systems with a much higher packaging efficiency, measured both in terms of density per unit area and per unit volume.

The second session reviewed TSV-3D applications and production scenarios with presentations by Hirofumi Nakajima, NEC (Japan), Claudius Feger, IBM (USA), Bernd Roemer, IFX (Germany), Caroline Beelen-Hendrikx NXP (Belgium) and Jacques Ferrara, ST Micro (France). Their presentations indicated that application drivers for 3D technologies are numerous and diverse. Among the top drivers were reduced size and form factor, which are obvious ones, but there are others drivers as well.

For example, device bandwidth and clock frequency are basically “flat-lining” in the world of 2D interconnections, and there is a need for more heterogeneous integration including RF, analog, logic, memory and sensors. Another driver is power reduction in an increasingly power hungry world. Other advantages include modularity and the potential of IP re-use to lower time-to-market and cost.

In summary, 3D technology is definitely on the rise both figuratively and literally, but there are many hurdles still to clear and much understanding still required. The technology resides largely in the domain of research but is rapidly moving to production. It seems clearly to be headed to a bright future, but its success will be gated by the quality of the communications that are employed to carry forward and codify the lessons learned.

Just as I’d hoped, it seems as though Françoise in 3D is becoming more than just a blog, but also a forum for the 3D community to contribute information. Keep it coming! — F.v.T

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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