It’s going to be a busy 3D week here at IMAPS Device Packaging Conference, in Scottsdale AZ. So I’m going to attempt to keep up with everything with short, daily blog posts. I can’t promise to cover everything in detail (hey, if you wanted that, you should have come yourself!) As I’ve said in the past, if you attend a number of conferences each year on a topic, you tend to hear a lot of repeat information. And with the snail’s pace of new technology adoption in the industry – it gets awfully redundant to keep writing the same thing over and over, so I’m going to try and spare 3D InCites readers from that and assume you all know the basics (market drivers, remaining technology challenges, need for standards, etc) and instead try to deliver what strikes me as new information. Let’s see how this goes.
Today’s keynote speaker, Nick Kim, of Hynix Semiconductor, gave the usual general overview of challenges the industry faces with adoption of 3D TSVs and 2.5D technologies. The difference this time was Kim’s announcement that for Hynix, production of 3D devices is no longer a matter of if but when and how. Still, I wonder about the seeming contradictory messages that challenges and issues remain, but ramping to HVM will happen by late 2014. I guess what this means is that the performance needs solved by 3D make it a necessity and that despite the challenges, it’s all systems go.
We’ve been hearing that cost is the issue for a while, but usually without details. This time Kim provided a detailed cost breakdown illustrating why 3D TSV stacks are more expensive (1.3x more) than wire bond stacks to manufacture. According to Kim, cost innovation is required for mass production. Overall, TSVs alone add 25% to the manufacturing cost because there is additional cost at each step:
- Design: net die area decreases due to TSV array.
- Fab: increased process steps due to TSVG formation, and capex for TSV equipment.
- Packaging: Bumping, stacking, low yield and capex for backside processing equipment such as temporary bond and debond.
- Test: Probe and final package test time is increased because of the need to test at each layer as well as final.
Kim said that critical to lowering cost will be depreciation (of equipment) and improved yield. Design optimization will help as well as reducing process turn-around time to increased productivity. He shared Hynix 3D roadmap, saying that volume TSV production will officially start after 2013:
- DRAM on Logic for mobile applications in a known good stacked die (KGSD) driven by form factor and power, are in development in 2012 with low production expected early 2013 ramping to volume late 2014.
- DRAM on interposer in a 2.5D configuration for graphics applications, driven by bandwidth and capacity is in development in 2012 with low production expected by the end of the year and ramping to HVM early in 2014.
- 3D DRAM on substrate for high performance computing (HPC) driven by bandwidth and capacity is in development in 2012, with low production expected early 2013, ramping to volume late 2014.
That’s it for today. A little preview for what’s to come later this week: a review of tonight’s 3D panel discussion and technology advances in glass interposers, and who knows what else! ~ F.v.T.
