MonolithIC 3D Inc., a Silicon Valley startup, announced today that it has been issued its fifth patent on monolithic 3D-IC technology. The patent describes techniques to obtain low-cost monolithic 3D logic chips with single crystal silicon transistors and high vertical connectivity. In addition to the 5 issued patents, the company has more than 50 other patents pending, making it one of the key pl... »
Applied Materials, Inc. today announced a breakthrough technology for reducing power consumption in semiconductor chips with its new Applied Producer® OnyxTM film treatment system. By optimizing the molecular structure of the low k films that insulate the miles of wiring, or interconnects, on each chip, the Producer Onyx system enables customers to continue their relentless drive to fabrica... »
Paul Enquist, Ziptronix Inc.’s chief technology officer and vice president of R&D, will provide an update on direct bond technology for 3-D ICs on Dec. 14 at the RTI conference on 3-D Architectures for Semiconductor Integration and Packaging in Burlingame, Calif. His presentation, “Applications Driving Adoption of Low Temperature Direct Bond Technology for 3-D Integrated Circuits,” ... »
We’ve been hearing so much lately from the 3D integration cheering section, that it’s actually hard to believe that there are folks who remain skeptical to the inevitability of 3D integration as a mainstream technology. But on December 6, during the evening 3D panel session at the 2011 IEDM, held at the Washington Hilton, Washington DC, we can expect it to all be laid on the line. In what pro... »
SEMATECH’s 3D Enablement Center (3D EC), together with the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), has identified the top technical challenges for new “killer” applications to enable future development of heterogeneous 3D integration beyond mobile wide I/O DRAM. Following the introduction of the wide I/O DRAM, further research and development o... »
The partners in a new European research project today announced details of the multinational/multidisciplinary 'SMArt systems Co-design' (SMAC) program. This important three-year project, partially funded by the EU's FP7 (FP7-ICT-2011-7), aims to develop a leading-edge design and integration environment (the 'SMAC Platform') for the design of smart systems. These are intelligent, miniaturized d... »
Two weeks ago, wearing my Chip Scale Review Sr. technical editor hat, I attended (along with 11 other journalists) an exclusive press conference launching a new electronic interconnect company, Deca Technologies, which claims to have developed disruptive manufacturing processes based on its sister company, SunPower’s, solar cell wafer processes, rather than traditional semiconductor manufacturin... »
All Silicon System Integration Dresden (ASSID), a leading-edge microelectronic wafer-level packaging and system integration center operated by the Fraunhofer IZM Institute, has begun pilot-line production of 3D semiconductor devices using a single-wafer, multi-chamber AltaCVD 300 system from Altatech Semiconductor S.A. At Fraunhofer IZM-ASSID’s 970-square-meter cleanroom facility in Dresden, Al... »
With all the latest hubbub about FinFets (or as Intel calls them, TriGate transistors) , there seems to be some confusion in terminology, leading to confusion in who’s doing what first. First and foremost, the technology Intel claims to have pioneered is 3D transistors, also known generically as FinFets. TSMC has also announced that they will move forward with FinFets. What people need to under... »
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