Sometimes I get so caught up in following the progress of 3D IC with TSV that I lose sight of what else is going on in the 3D space.That is until something like STATS ChipPAC’s announcement that they are ramping to volume production with first-generation eWLB technology hits my inbox. »
I just took a good look at the line-up for the 3-D Architectures for Semiconductor Integration and Packaging, coming up December 9–11, 2009, and I think I might have died and gone to 3D heaven. You want to know who the movers and shakers are in this space? They’re all here, and they’ll be addressing all the critical issues we’ve been hearing so much about: design, test and thermal issues,... »
As part of the 3D tracks at both this year’s International Wafer Level Packaging Conference, held October 27-30 in Santa Clara, CA; and the 2009 IMAPS International Symposium, held Nov 3-5 in San Jose, CA, several suppliers offered up solutions addressing current limitations in via etch, insulation/barrier/seed layers, and fill process steps for 3D TSVs. »
I have to admit, I’ve always had difficulty trying to wrap my head around software, especially design tools. So I’ve come to have a deep respect for those individuals charged with the task of designing the design tools themselves. Not only do they need to be able to visualize the end result, they have to work backwards to anticipate the steps required to get there, and then figure out a way to... »
I’m glad I stuck around last evening for the 3D panel discussion on the status of 3D integration technologies, applications and roadmaps. As moderator Phil Garrou pointed out, it offered the opportunity to hear some commentary I might have otherwise missed by only attending the scheduled presentations. As a result, I, and a roomful of active participants, got a peek at the inside track of whatâ€... »
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