system-level design

Why is it Taking so Long to Ramp Interposer and 3D IC Designs?

Why is it Taking so Long to Ramp Interposer and 3D IC Designs?

And what are we going to do about it in 2015…? A moment ago I finished reading my predictions for 2014. I wrote them on January 11, 2014, almost exactly one year ago. After convincing myself that I was roughly on target, I am going to stick my neck out again, and, hopefully, give you some food for thought. I hope you can agree with me that my previous predictions, emphasizing good prospects for... »

Courtesy of Cadence - 3D By Design

3D By Design: A Blog By and For the 3D Design Community

Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D integration technologies as a solution to dealing with the increasing complexity of SoC designs. The post was inspired by my attendance at the Design and Test Europe (DATE 2014) conference, where I moderated a session on system on chip (SoC) design complexity, and ... »

Are Chip Architects Finally Climbing on the 2.5D and 3D Bandwagon?

Are Chip Architects Finally Climbing on the 2.5D and 3D Bandwagon?

Ever since SEMICON West 2014, I’ve been seeing a lot of coverage of the 2.5D and 3D adoption question on Semiconductor Engineering, an industry content platform that covers the spectrum of semiconductor topics, and occasionally covers 2.5D and 3D, providing the perspective of chip architects, engineers, end users, industry organizations and standards bodies. What I find most interesting in these... »