3D SOC

The Edge of 3D: 3D SoC VLSI and Si Photonics

The Edge of 3D: 3D SoC VLSI and Si Photonics

Last week, I posted an executive summary of this year’s European 3D Summit, touching on the highlights and general takeaways based on the closing remarks I delivered at this year’s well-attended event, which took place January 23-25, 2017 at Minatec Campus in Grenoble. In this post, we’ll take a deeper dive into some of the edgier technologies in development that were presented, and what is ... »

Xilinx Ultrascale+: 3D on Steroids

Xilinx Ultrascale+: 3D on Steroids

Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family of 3D integration technology possibilities, we’ve been careful to define them separately on 3D InCites. Some people have wondered if one will displace the other, or if these technologies would delay the adoption of 3D stacked ICs using TSVs. I maintain that these technologies h... »

Courtesy of Cadence - 3D By Design

3D By Design: A Blog By and For the 3D Design Community

Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D integration technologies as a solution to dealing with the increasing complexity of SoC designs. The post was inspired by my attendance at the Design and Test Europe (DATE 2014) conference, where I moderated a session on system on chip (SoC) design complexity, and ... »

SEMICON West 2014: Are 3D ICs Getting the Squeeze?

SEMICON West 2014: Are 3D ICs Getting the Squeeze?

With the continued innovations in packaging technologies and 2.5D interposers pushing 3D ICs further out from one end, and 16/14nm nodes already qualified without TSVs, making us wait until 10nm, are 3D ICs suddenly getting the squeeze from both sides? That’s one theory I took away from all the conversations and presentations at this year’s SEMICON West 2014, which took place July 7-10, 2014 a... »

Having the Courage to Design in 3D TSVs

Having the Courage to Design in 3D TSVs

I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I think Ron Huemoeller, Amkor, finally hit on it in his closing remarks during today’s webcast, “TSV Packaging at the Tipping Point”, moderated by Pete Singer, Solid StateTechnology/Extension Media. Huemoeller’s presentation and that of David Butler, SPTS, once again reinforced wha... »

Is the Road to 3D ICs Paved with 3D SOC?

Is the Road to 3D ICs Paved with 3D SOC?

Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its name is 3D SoC (aka: 3D system on a chip, or 3D system partitioning, or mixed node integration – take your pick). Whatever the moniker, it looks like THIS is going to be the one to remember most, as its likely to finally provide the technology/cost advantage that makes 3D ICs worth ... »

Getting the picture in 3D

When you’re totally immersed in any one topic, and therefore listen to nothing but presentations about novel processes, solutions, progress, innovations, equipment advancements on said topic for days at time, you start to hear A LOT of the same stuff over and over again. You assume everyone else has heard the same thing, until you realize that if this is their first presentation on said topic, t... »