Presentations

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a greater number of I/O contacts, at a lower cost. With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers, and power management ICs in mold wafers, thereby enabling the latest generation of ultra-thin w... »

Direct Bond Interconnect (DBI®) Technology as an Alternative to Thermocompression Bonding

Direct Bond Interconnect (DBI®) Technology as an Alternative to Thermocompression Bonding

The industry standard interconnect technology for fine-pitch 2.5D assembly and 3D stacking is thermocompression bonding of solder capped μbumps. This technology has several challenges which have limited widespread adoption in high-volume production. While the implementation of the technology at 40μm pitch is already challenging, the likelihood of extending this technology to 10μm pitch is slim,... »

Package-on-Package Interconnects for Fan-out Wafer Level Packages

Package-on-Package Interconnects for Fan-out Wafer Level Packages

Consumer electronics designers continue to demand thinner and lighter packages while devices increase in functional complexity. The Fan-Out Wafer Level Package (FOWLP) platform has been gaining momentum with the advantages it offers in electrical performance, assembly process efficiency and low geometric profile.  Different approaches of Package-on-Package (PoP) stacking in FOWLP have been develo... »

Micro and Nano X-ray Tomography of 3D IC Stacks

Micro and Nano X-ray Tomography of 3D IC Stacks

Advanced packaging, and particularly 3D through silicon via (TSV) integration technologies and the resulting 3D-stacked products, challenge materials and process characterization. For 3D TSV stacking of wafers or dies, die-to-die interconnections like micro solder bumps (e.g. AgSn) and Cu pillars are used. The control of the TSV filling and micro-bump quality is a particular issue. In this present... »

Fraunhofer EMFT: Our Early and Ongoing Work in 3D Integration

Fraunhofer EMFT: Our Early and Ongoing Work in 3D Integration

Fraunhofer has been working on 3D integration for the past three decades, starting in1987 with a consortium of Siemens, AEG, Philips and the Munich institute IFT (now EMFT).  By 1988, we could successfully fabricate 3D CMOS devices based on recrystallization of deposited poly-Si. In the mid-1990s, we developed a complete process flow for “Through-Si Via technology (TSV) in close cooperation ... »

TSV Technology Trends and Fabrication Details: A Short Course

TSV Technology Trends and Fabrication Details: A Short Course

3D/TSV technology has been the subject of intense development over the last 10-15 years. During this time, many process advancements were made and several basic questions were answered regarding when and how TSVs would be integrated. After tremendous progress on the technology side, much of the current focus is on 3D product launches and remaining commercialization issues, primarily cost reduction... »

How 2.5/3D Technologies Will Shake Up the Semiconductor Supply Chain and Cost Structure

How 2.5/3D Technologies Will Shake Up the Semiconductor Supply Chain and Cost Structure

At the 2015 3D InCites Awards Breakfast, which took place July 16, 2015 at the Impress Lounge during SEMICON West, Scott Jones, Director, Alix Partners presented a talk in which he described the positive financial impact interposer and 3D integration will have on the semiconductor manufacturing supply chain. He suggested we think like a fab owner when considering the benefits of implementing in... »

The Internet of Things and Semiconductor Test

The Internet of Things and Semiconductor Test

Herb Reiter, eda2asic, presented this poster presentation titled “The Internet of Things and Semiconductor Test” at the Test Vision 2020 Workshop during Semicon West 2014. Here is the printed transcript of the talk. The accompanying slides referenced in the text can be downloaded as well. In the 1990s cell phones started to connect people wirelessly and changed the way of verbal commun... »

Survey and Review of  2.5D and 3D IC Packaging Technologies

Survey and Review of 2.5D and 3D IC Packaging Technologies

On April 9, 2014 Herb Reiter presented a 2.5D and 3D IC packaging-centric update in context with an IEEE/CPMT dinner meeting at the Biltmore Hotel in Santa Clara. About 50 silicon-, packaging-, assembly and test experts attended this 1-hour presentation. Most of them stayed for the very interactive Q & A session, that turned out be last another hour. In his presentation, Reiter discussed ̶... »