3D InCites Technical Advisory Board
Sitaram R. Arkalgud, Ph.D., VP of 3D Technology, Invensas Corp. San Jose, CA
Sitaram Arkalgud is Vice President of 3D Technology at Invensas Corporation, a complete Interconnectology solutions provider for advanced mobile applications. Previously, Arkalgud started and led 3D IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. In addition, he has worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. Arkalgud holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. He is the author of several publications and holds 14 U.S. patents.
Rozalia Beica, CTO, Yole Développement
Rozalia Beica leads the Advanced Packaging Business Unit and Semiconductor Manufacturing activities within the market research firm, Yole Développement. Beica is an international award (R&D 100) winning scientist with over 60 publications and several patents. For more than 16 years, Rozalia has been involved in the research, application and strategic marketing of Advanced Packaging and 3D IC technologies, with global leading responsibilities at materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. She has a Global Executive MBA from IE Business School (Spain), M. Sc. In Management of Technology from KW University (USA) and a B.Sc/M.Sc in Chemical Engineering from Polytechnic University “Traian Vuia” (Romania)
Yann Guillou, Business Development Manager, SEMI Europe Grenoble Office, France
Yann Guillou is Business Development Manager at SEMI Europe Grenoble Office. His main responsibilities encompass the development of SEMI activities in France & Southern Europe in Semiconductor, PV and Emerging markets and the coordination of SEMI standard activities in Europe. Previously, Yann worked on Advanced Packaging activities within the Back-End Sourcing and CTO & Strategic Planning office of ST-Ericsson. His main interest was 3D integration and TSV. He started his career at CEA-Leti before joining ST Microelectronics and successively worked at ST-NXP Wireless and ST Ericsson. Yann holds an MS in materials and nanotechnology from the National Institute of Applied Sciences and a master of management of technology and innovation from Grenoble Business School.
Erik Jan Marinissen, Principal Scientist at IMEC, Leuven, Belgium
Erik Jan Marinissen focuses his research in the domain of test and debug of integrated circuits. He is a co-author of more than 120 journal and conference papers and a co-inventor of eight granted US and EU patent families. Prior to IMEC, he was with NXP Semiconductors and Philips Research, both in Eindhoven, The Netherlands. He has received numerous awards for his work, including the Most Significant Paper Award at the IEEE International Test Conference in 2008. Marinissen served as an Editor-in-Chief of IEEE Std. 1500. He serves on numerous conference committees and editorial boards, and founded such workshops as ‘Diagnostic Services in Network-on-Chips’ (DSNOC) and ‘3D Integration’. He is a Senior Member of IEEE and a Golden Core Member of Computer Society. Marinissen holds a MSc degree in Computing Science a PDEng degree in Software Technology from Eindhoven University of Technology.
Peter Ramm, Department Head, Heterogenous Systems Integration, Fraunhofer EMFT, Munich, Germany
Dr. Peter Ramm is responsible for the key competence “Si Processes, Device, and 3D Integration”. He received physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is author or co-author of over 100 publications and 24 patents. He received the “Ashman Award 2009” from the International Electronics Packaging Society (IMAPS) “For Pioneering Work on 3D IC Stacking and Integration and leading-edge work on SiGe and Si technologies”. Peter is Fellow and Life Member of IMAPS, organizing committee and founding member of IEEE 3DIC conference and co-editor of Wiley´s “Handbook of 3D Integration”, vol. 1, 2 & 3 and Wiley´s “Handbook of Wafer Bonding”.
Herb Reiter, Founder, eda2asic Consulting, Palo Alto, CA
After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role, Herb introduced innovative IC design tools to the major semiconductor vendors worldwide. In 2008 he expanded his scope into Multi-die ICs. As chair of the GSA’s 3D-IC Working Group (2008-2011) and as SEMATECH business development consultant (2012 + ‘13), he broadened his horizon to include interposers and 3D-ICs technology, semiconductor materials as well as manufacturing, metrology and test equipment. In 2014 + ’15 Herb consulted with Si2, to encourage development and standardization of data exchange formats for Interposer and 3D-IC design flows. Since early 2016 he is consulting with the newly formed Electronic System Design Alliance (formerly EDAC), to accelerate market acceptance of Multi-die ICs, the essential building blocks for the emerging System Scaling methodology.
Mark Scannell, Director Business Development Silicon Component Division, Leti, Grenoble, France
Mark Scannell has an engineering degree from National University Ireland. He has 25 years experience in the electronics and semiconductor industry. Starting his career as an electro-mechanical design engineer in 1989; he subsequently worked for one of the world’s leading semiconductor equipment suppliers in various engineering positions and as a technology business director. Mark has lived in several countries; notably Japan, Germany, USA, and France. He joined CEA – Léti in 2005. Mark’s current position is Business Development Director where his responsibilities include business development for silicon components, industrial contracts, and IP management.
Larry Smith, Ph.D., Independent Consultant, 3D TSV Technologies, Albany, NY
Larry Smith previously managed the TSV module in SEMATECH’s 3D Associate Member Technology Development Program. His responsibilities have also included SEMATECH’s 3D Enablement Center, TSV integration and reliability, cost and yield modeling, test vehicle design, and ULK reliability. He has chaired several workshops on critical 3D issues, including Reliability and Manufacturability, Design and Test, Stress Management, and ESD. Prior to joining SEMATECH, he managed the design group for thin-film-on-laminate (XLAM) BGA substrates at Kulicke and Soffa, and programs on multi-chip packaging at MicroModule Systems, Dell Computer, and MCC. Dr. Smith received his B.S. from MIT, his Ph.D. from the University of Illinois, and was a Research Fellow at Harvard University (all in Physics), and developed high-speed digital and analog superconductive devices at the Sperry Research Center and the MIT Lincoln Laboratory.
E. Jan Vardaman, president and founder of TechSearch International, Inc., Austin, TX
E. Jan Vardaman founded TechSearch International Inc. in 1987, and since then has provided licensing and consulting services in semiconductor packaging. She is the co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly/Printed Circuit Board Fabrication, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, SMTA, MEPTEC, IPC, IMAPS, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She has made numerous presentations on developments in advanced packaging.
Paul Werbaneth, Global Product Marketing Director, Intevac, Inc.
Paul Werbaneth is the Global Product Marketing Director at Intevac, Inc. Since entering the semiconductor industry in 1980 he has been a hands-on Photolithography Process Sustaining Engineer in an Intel wafer fab; a Senior Plasma Etch Process Engineer with Hitachi High Technologies; the Country Manager for Tegal Japan Inc.; the Vice President of Marketing and Applications at Tegal Corporation; a Business Development Manager at EV Group; and an independent consultant and writer. Paul is a member of the SEMI Advanced Semiconductor Manufacturing Conference steering committee and was the ASMC 2004 Conference Co-Chair. He also serves on the steering committee for the NCCAVS Thin Film User Group. Paul’s writing activities include his frequent contributions on heterogeneous integration and 2.5-D/3-D IC technology and commercialization to 3D InCites; his work as a Guest Editor for IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING; the contributed chapter on TSV etching in the book 3D Integration for VLSI Systems. Follow him on Twitter @PFWerbaneth.
M. Juergen Wolf, Head of Division Wafer Level System Integration, Fraunhofer IZM-ASSID
M. Juergen Wolf studied electrical engineering and after an industrial career, he joined Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin in 1994 working in the field of wafer level packaging and System in Package (SiP). Since 2011 he is head of department Wafer Level System Integration and also responsible for the management of ASSID – “All Silicon System Integration Dresden-ASSID” with its 300 mm 3D Wafer Level Integration line. He is also involved in and leading a number of research projects on the national, European and international level. Wolf is, among others, a European representative in the technical working group Assembly & Packaging of ITRS, a board member of EURIPIDES and JISSO as well as a member of IEEE and SMTA. He has authored and co-authored numerous scientific papers and reports in the field of microelectronic packaging and holds a number of patents.