2014 3D InCites Award Judges
The 2014 3D InCites Awards Judges represent each part of the 2.5D/3D IC ecosystem. This year’s panel has been expanded to include industry, academia, and R&D, as well as experts in design, test, processes, and manufacturing.
Sitaram R. Arkalgud, Ph.D., VP of 3D Technology, Invensas Corp.
Sitaram Arkalgud is VP of 3D Technology at Invensas Corporation, a complete Interconnectology solutions provider for advanced mobile applications. Previously, Arkalgud started and led 3D IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. In addition, he has worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola.
Yann Guillou, Business Development Manager, SEMI Europe Grenoble Office
Yann Guillou is Business Development Manager at SEMI Europe Grenoble Office. His main responsibilities encompass the development of SEMI activities in France & Southern Europe in Semiconductor, PV and Emerging markets and the coordination of SEMI standard activities in Europe. Previously, Yann worked on Advanced Packaging activities within the Back-End Sourcing and CTO & Strategic Planning office of ST-Ericsson. His main interest was 3D integration and TSV. He started his career at CEA-Leti before joining ST Microelectronics and successively worked at ST-NXP Wireless and ST Ericsson.
Erik Jan Marinissen, Principal Scientist at IMEC
Erik Jan Marinissen focuses his research in the domain of test and debug of integrated circuits. He is a co-author of more than 120 journal and conference papers and a co-inventor of eight granted US and EU patent families. Prior to IMEC, he was with NXP Semiconductors and Philips Research, both in Eindhoven, The Netherlands. He serves on numerous conference committees and editorial boards, and founded such workshops as ‘Diagnostic Services in Network-on-Chips’ (DSNOC) and ’3D Integration’.
Phil Marcoux, PPM Associates
Phil’s efforts in 2.5D and 3D packaging represent his fourth major new business development. He has been a pioneer in laser trimmed IC devices, surface mount technology, wafer level packaging and now 3D. A common thread in his involvement is multi-chip packaging.
Herb Reiter, eda2asic
After 20 years in technical and business roles at large semiconductor vendors, Herb Reiter changed to the EDA side to help narrow the gap between EDA tools’ productivity and IC designers’ requirements. Since 2008 Herb has focused his efforts with EDA vendors, large semiconductor companies and IP and design service firms in contributing to the 3D/TSV ecosystem to accelerate market acceptance of this new technology.
Ira Feldman, Principal Consultant, Feldman Engineering Corp.
Ira Feldman manages and develops unique high technology solutions and business strategies for clients of Feldman Engineering Corp. His goal is to resolve product management and engineering challenges within organizations as well as with their supply chain and customers. His broad knowledge and management experience with high-volume manufacturing of complex technology products is the result of extensive expertise in the semiconductor test and computer test industries.
Paul D. Franzon, Alumni Distinguished Professor of ECE. North Carolina State University
Paul D. Franzon, Ph.D. is currently a Professor of Electrical and Computer Engineering at North Carolina State University. His current interests center on the technology and design of complex systems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, PBI Inc., Communica and LightSpin Technologies.
Paul S. Ho, Director, Laboratory for Interconnect & Packaging, University of Texas at Austin
Paul S. Ho, Ph.D. has been on the faculty at The University of Texas at Austin since 1991, when he was appointed the Cockrell Family Regents Chair in Materials Science and Engineering. His current research is in the areas of materials and processing science for interconnect and packaging for microelectronics. He has 20 years of industrial experience working at the IBM Thomas J. Watson Research Center, New York.
Urmi Ray, Ph.D, Senior Staff Engineer Qualcomm
Urmi Ray, Ph.D. is the technical program manager for Qualcomm’s Through Silicon Stacking (TSS) program and is also leading a program on low-cost interposer technology. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in the 3D technology area.
Peter Ramm, Department Head, Heterogenous Systems Integration, Fraunhofer EMFT
Peter Ramm is responsible for the key competence “Si Processes, Device and 3D Integration”. He received physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is author or co-author of over 100 publications and 24 patents.
Mark Scannell, Director Business Development Silicon Component Division, Leti
Mark Scannel is responsoble for business development for silicon components, industrial contracts and IP managemen at LETI. He has 25 years experience in the electronics and semiconductor industry. Starting his career as an electro-mechanical design engineer in 1989; he subsequently worked for the one of the world’s leading semiconductor equipment suppliers in various engineering positions and as a technology business director. He joined CEA – Léti in 2005.
Paul Siblerud, Founder & CEO, Strategic Tech Analysis
Paul Siblerud is the CEO of the competitive analysis company Strategic Tech Analysis LLC. Previous to starting the consulting firm, Siblerud worked at Semitool for 20 years in product management and marketing with the electroplating group. In Semitool, he worked on equipment and processes for advanced Wafer Level Packaging (WLP), copper and Thru-Silicon-Via (TSV) technologies. During his tenure, he founded the WLP consortium SECAP and TSV consortium EMC-3D.
Larry Smith, Ph.D. Independent Consultant, 3D Integration Technologies
Larry Smith has worked on 3D IC technologies at SEMATECH as manager of the 3D Enablement Center, a broad-based consortium tackling 2.5D and 3D ecosystem readiness in the areas of reference flows, key challenges, standards, inspection & metrology, material and assembly landscapes, and SRC sponsored research. Previous to this role, he was responsible for TSV integration and reliability, cost and yield modeling, test vehicle design, and roadmapping.
Paul Werbaneth, 3D and MEMS Industry Journalist, Petaluma CA
Paul Werbaneth writes regularly for 3D InCites on 2.5D/3D IC technology and commercialization. He is a guest editor for IEEE Transactions on Semiconductor Manufacturing, and contributed a chapter on TSV Etching in the book “3D Integration for VLSI Systems,”. Paul has worked as a business development manager at EV Group; vice president of marketing and applications at Tegal Corporation; country manager for Tegal Japan Inc.; senior plasma etch process engineer with Hitachi High Technologies; and as a hands-on process sustaining engineer in an Intel wafer fab.
M. Juergen Wolf, Head of Division Wafer Level System Integration, Fraunhofer IZM-ASSID
M. Juergen Wolf studied electrical engineering and after an industrial carrier, he joined Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin in 1994 working in the field of wafer level packaging and System in Package (SiP). Since 2011 he is head of department Wafer Level System Integration and also responsible for the management of ASSID – “All Silicon System Integration Dresden-ASSID” with its 300 mm 3D Wafer Level Integration line. He is also involved in and leading a number of research projects on national, European and international level.