Consumer electronics designers continue to demand thinner and lighter packages while devices increase in functional complexity. The Fan-Out Wafer Level Package (FOWLP) platform has been gaining momentum with the advantages it offers in electrical performance, assembly process efficiency and low geometric profile. Different approaches of Package-on-Package (PoP) stacking in FOWLP have been developed with some approaching high volume production recently. This presentation presents a review of the common configurations of stacked FOWLP with a specific focus on PoP interconnects and their compatibility with the different process options. The feasibility of incorporating low-cost Bonded Via Array (BVA®) as one of the PoP interconnect options is also discussed.
BVA as a PoP interconnect option in FOWLP can be incorporated into either a chip first or a chip last FOWLP PoP approach. In this presentation, the materials and process details describing BVA bonding onto a conventional Redistribution Layer (RDL) build-up structure are discussed, and the bonding feasibility is demonstrated.
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This was presented as part of the 2016 International Wafer-level Packaging Conference, October 18-20, 2016
