TSV MEOL Process Flow for Mobile 3D IC Stacking

Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions. Wide band transmission between logic and memory is becoming indispensable for not only mobile products, but also other products related to network systems such as servers and data centers. These days, 3D integration with Through Silicon Vias (TSVs) is considered as the key solution, which brings benefits leading to low power consumption and product downsizing.

This paper mainly describes 3D TSV packaging technologies used in mobile 3D-IC stacking, especially MEOL processes, package assembly, and its reliability. To prove the quality of this 3D package, component and board-level reliability tests were conducted to evaluate the reliability at the package level. Finally, a 28nm logic device and Wide I/O DRAM were assembled into a 3D structure to demonstrate functionality of this new technology.

3D Advanced Wafer Level Packaging (WLP) Evolution
The need for higher levels of integration, improved electrical performance, reduction of timing delays, and shorter vertical interconnects is driving a shift from 2D to 2.5D and 3D package designs. 3D integration is proceeding on three fronts — moving from package level (die and package stacking) to wafer level (especially fan-out wafer level packaging (FOWLP), and, more recently, to the silicon (Si) level with TSV and interposers. Today’s lightweight mobile products are innovative devices providing true convergence with powerful computing functions, high speed communications, and visual, sensing, and imaging technologies. This convergence is pushing traditional packaging well beyond its typical limits in the areas of form factor, reliability and performance (Figure 1).


Figure 1: Emerging technology trends for the mobile marketplace.

3D Test Vehicle (TV) Design and Details
The target 3D vehicle consisted of Wide I/O DRAM with micro-bumps, the logic device with high density TSVs and fine pitch Cu pillars and an organic substrate, as shown in Figure 2. Non-conductive paste (NCP) was adopted as an underfill material to protect flip chip joints between the logic die and the substrate.


Figure 2. Schematics TSV 3D IC stacking.

Table I summarizes major specifications of the logic TV, the memory TV and the substrate. They were designed to clarify behaviors of the 3D structure in the following reliability tests.


Table I. Specifications of logic and memory TV

3D TSV MEOL Process
The TSV MEOL process flow occurs between the wafer fabrication and back-end assembly process (Figure 3). MEOL processes support the advanced manufacturing requirements of 2.5D and 3D TSV as well as wafer level packaging, flip chip and embedded die technology.


Figure 3. MEOL and package assembly steps in overall 3D TSV process flow.

Copper Column Micro-bump Process
Wide I/O micro-bumps using JEDEC 42.6 standards,have 50/40µm bump pitch in x/y direction, respectively. Cu columns with solder cap micro-bumps have been studied with the objective to develop reliable fine-pitch solder micro joints at low cost. SEM micrographs of micro-bumps are shown in Figure 4 for 20μm diameter and 40μm height micro-bumps for 80/40μm staggered bump pitch.


Figure 4. Micrograph of Cu column micro bump.

Backside Via Reveal (BVR) Process
As shown in the 3D TSV process flow of Fig.3, TSVs are revealed on the wafer backside to create a 3D vertical interconnection after front-end TSV formation. Using a temporary bonding/debonding system, a TSV wafer from the fab must be thinned-down and Si etched to expose the Cu via using fab processes. The Cu TSV was fully protected through a highly selective Si etch process to assure there was no Cu contamination (Figure 5). There was also Time-of-Flight Secondary Ion Mass Spectroscopy (TOF SIMS) analysis for detecting Cu contamination on the Si wafer during the Chemical Mechanical Polishing (CMP) process. This verified non-detectable Cu content after chemical composition analysis was performed along the whole 300mm TSV wafer. FIgure 6 shows total thickness variation (TTV) of a 3D TSV wafer after BVR process. It showed only a few microns of TTV values on 300mm test vehicles after process optimization with several design of experiments (DOEs).


Figure 5. FIB SEM micrographs of protective Cu TSV BVR process.


Figure 6. Total thickness variation (TTV) of revealed TSV wafer with temporary bonding.

3D TSV Assembly and Packaging
Flip chip assembly was carried out to establish the bonding process and investigate the reliability with Cu pillar micro-bumps. After fabrication of bumps on the micro-bump test vehicle, the flip chip attachment was carried out. Several DOEs were carried out to determine the optimized flip chip attach process conditions as functions of time, temperature, and pressure. Assessments were conducted by checking the fractural surface and mechanical shear strength to evaluate DOEs of bonding parameters. Figure 7 shows cross-section micrographs of the chips joined using 40μm pitch micro-bumps. A misalignment of about <2μm was observed between the Si chip and 3D TSV chip after assembly. This misalignment was a result of accuracy limitations of the bonder equipment. After assembly, X-ray images showed successful 3D TSV flip chip bonding without voids in between chip-to-chip, chip-to-substrate, respectively.


Figure 7: Micrographs of (a) cross-section of 3D IC stacking and (b,c) 40/80 μm pitch of chip-to-substrate bonding.

Electrical Performance Validation
To evaluate actual performances of the unique assembly process developed in this study, a 3D package that combines 28nm logic and Wide I/O DRAM was assembled. This 3D package had the extremely small logic device as a bottom die and the large memory device as a top die. The memory device was a 4 Gbit 512 DQs monolithic Wide I/O DRAM, with a size of 9 x 9 mm² and a thickness of 260μm. After the assembly, electrical performances of the samples were evaluated with LSI testers. Not only the 1200 TSVs connectivity, but also DRAM bit quality, at speed test, current consumption were investigated carefully. In conclusion, it was proven that the test vehicle achieved 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3.

Component and Board-level Reliability
Table II summarizes the stress conditions and results. Before the reliability tests, all samples were treated with the moisture sensitivity level 3 (MSL3) (30oC /60% RH, 168h) and reflowed three times (a peak reflow temperature: 260oC). In this test vehicle, daisy chains were laid out to evaluate the connections among the logic die, the memory die and 1200 TSVs. The resistance of each daisy chain was measured periodically in all test items. Board-level reliability tests were also carried out as shown below in Table II.


Table II. Test items and results of package and board level reliability tests.


  1. Innovative assembly of 3D TSV MEOL and package assembly technology has been developed for reliable 3D/TSV integration.
  2.  Cu pillar bump, temporary bonding/debonding and BVR process were optimized and qualified with 300mm daisy chain and 28nm functional wafers.
  3. Package assembly stacking process was established for chip-to-chip, chip-to-substrate interconnection with thermocompression bonding with 40/50µm ultra-fine pitch micro-bump.
  4. All of the samples passed 1500-cycle TC, 1000h HTS, 1000h HT, 500h uHAST and 300h PCT and board level reliability including TCoB and bending tests.
  5.  3D test vehicle showed 12.8GB/s transmission and 89% reduction of I/O power consumption compared to LPDDR3. As a result, the robust process for 3D integration was established.


  • Seung Wook Yoon, STATS ChipPAC Ltd, 10 Ang Mo Kio Street 65 Techpoint #05-17/20 Singapore 569059
  • Duk Ju Na, Kyaw Oo Aung, Won Kyung Choi, Andy Chang Bum Yong, STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
  • Tsuyoshi Kida, Toshihiko Ochiai,Tomoaki Hashimoto, Michitaka Kimura, Keiichirou Kata, Renesas Electronics Co., 1753, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa 211-8668, Japan

This article was based on a white paper that was presented at ECTC 2014 titled, TSV MEOL (Mid End of Line) and Packaging Technology of Mobile 3D-IC Stacking. 

1 Comment

  1. Dr. Dev Gupta - August 8, 2014, 3:21 pm Reply

    Could the authors please comment on the following :
    (1) were any stacks built with more than one memory die ?
    (2) did the Wide I/O memory chip(s) used follow the JEDEC Wide I/O 1 std. re: layout of the TSVs & Buffer design ?
    (3) was the data R/W in SDR or DDR mode ? Clock Rate ?
    (4) was Renesas the source for the Wide I/O DRAM ? Is it still an active program post acquisition by Micron whose HMC does not follow Wide I/O exactly
    (5) what were the major functional ( IP ) Blocks in the Logic die ? Did they have to be re arranged to conform to the central array of TSVs per JEDEC Wide I/O spec, any Redistribution ? perf. Penalties ?
    (6) was there any evaluation of stress on devices due to nearby Cu filled TSVs ?

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