SEMI 3D IC Standards Workshop at SEMICON Singapore 2014

SEMI 3D IC Standards Workshop at SEMICON Singapore 2014

SEMICON Singapore 2014 featured a Friday round-table workshop about SEMI 3D IC Standards, which was held to determine local needs for standardization for 3D integration activities, to channel that activity to the right standards organizations. The goal was to trigger a discussion around what the most important standards are for the Southeast Asia region.

3D IC SEMI Standards

Figure 1: SEMI’s James Amano discussed SEMI’s progress with establishing 3D IC Standards.

James Amano of SEMI started off with an overview of SEMI’s 3D standard activities. These activities started in 2010 and have resulted in a number of publications for 3D terminology: glass carrier wafers, metrology, TSV/CMP for micro-bump, alignment marks for 3DIC, glass interposers, etc. There are three SEMI groups working on these standard development areas located in the USA, Japan, and Taiwan. James stated he would like to start a group in Singapore. SEMATECH and SEMI have teamed up to create a website that will include all of the SEMI, IEEE, JeDEC, Si2 and the 3D Alliance activities. Currently the website is not up to date and they may have to transfer it to a new location. Suggestions for areas to be incorporated in future activities include:

  • Making sure customer needs are addressed
  • More focus put on the front-end standards and movement towards more complex test vehicles for in-line sampling to insure high yields. Suggestions include using a temporary interposer for die testing (KGD) and direct testing of the interposer prior to assembly.
  • Emphasis on test probe challenges for TSV and Si interposers
  • Standard for repair processes for interposers and 3D TSVs
Figure 2: Tim Linehan leading the discussion at the 3D IC Standards Workshop. Ramakanth Alapati, Global Foundries, was among the attendees.

Figure 2: Tim Linehan leading the discussion at the 3D IC Standards Workshop. Ramakanth Alapati, Global Foundries, was among the attendees.

Discussion topics included the need for answers to the known good die (KGD) issue, (solutions include BIST, etc.) and being able to test for all of the defects that needed to be screened. It would appear a front-end-of-line tester will eventually be needed in the back-end-of-line as many of the requirements will be the same, for example in RF applications.

The group concluded that specifications are needed for 3D reliability (electromigration, TSV’s, warpage, etc.), design rules running from the FEOL to the BEOL, and IBIS models for interposers. One participated stated that the industry has not reached high enough volumes to know what the problems are likely to be. ~ T.L.

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