Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires…

Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires…

True to form, Samsung followed up it’s V-NAND Flash announcement of 2013 with a product chip-level presentation at the 2014 IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco on February 12th. This provides the ideal opportunity to study the result of their work at the product level and compare with the predictions that I made in the Towering Spires or Costly Canyons series of posts.

Their presentation is entitled “Three-Dimensional 128Gbit MLC Vertical NAND (V-NAND) Flash-Memory with 24-WL Stacked Layers and 50MB/s High-Speed Programming” and has 46 authors in true space program fashion.

Let me begin by summarizing the facts as given in the presentation.

  1. 128 Gbit single chip
  2. Die size is 133mm2
  3. 40nm node
  4. 24 active cell layers along with 2 dummy cells and 2 select lines
  5. 2 electrical bits per physical cell
  6. Charge Trap Flash based.
  7. More than 5 generations envisaged to get to 1 Tbit on a single chip
  8. All generations will use the 40nm node
  9. Capacity increases to be achieved through further stacking of cells
  10. Defect issues need to be solved to improve 3D yields

Samsung’s achievement is a culmination of several years of work from many people in different engineering disciplines and certainly calls for hearty congratulations.

And after the clapping has subsided and after grumbling about the extensive use of normalized and arbitrary units, we need to assume once again our skeptical approach to be able to test the claims and projections made by the authors.

The main claim that needs to be probed is that V-NAND Flash technology has now been established as the viable successor to existing 2D NAND in that the next five technology generations can be built upon this foundation resulting ultimately in a 1 Tbit single chip NAND Flash.

Let me begin by listing five further bits of information not stated in the presentation but easily derivable.

  1. Die dimensions are ~ 11.8 mm by ~ 11.2 mm
  2. Array efficiency is ~ 80%
  3. Physical cell size on each layer is ~ 40300 nm2
  4. Physical cell dimensions are ~ 155 nm by ~ 260 nm
  5. 1 Tbit will need 192 active cells in a V-NAND string

The physical cell size will be approximate but close to reality. It will be the value at the top of the 24 layer stack since the tapering on the vertical slits and holes is not given. The array efficiency is also approximate but close to reality.

A generic vertical channel 3D NAND with approximate cell dimensions in red at the top of the stack derived from Samsung’s 2014 ISSCC presentation. The blue rectangle is the size of a 2D NAND cell at 40 nm node. The yellow rectangle is a 16 nm node 2D NAND cell.

Figure 1 – A generic vertical channel 3D NAND with approximate cell dimensions in red at the top of the stack derived from Samsung’s 2014 ISSCC presentation. The blue rectangle is the size of a 2D NAND cell at 40 nm node. The yellow rectangle is a 16 nm node 2D NAND cell.

Figure 1 shows a generic vertical channel 3D NAND at the top of the stack with the derived cell dimensions shown as a red rectangle. As in my previous posts, the green pillars represent the vertical channels (reality is more complicated with an additional inner dielectric pillar), the grey sheath is the charge trap dielectrics, and the red bars are the wordline gates.

The most important point to understand is how large the 3D NAND cell actually is. To illustrate this, figure 1 has two additional rectangles. The blue one is the approximate area taken up by a 2D NAND cell at the same node as the 3D NAND cell, namely 40nm. The yellow rectangle is the approximate area of a 2D NAND cell at the most aggressive node to date, namely 16nm. I have included details below of Micron’s 128Gbit at 16nm.

The 3D NAND cell is about 5 times the size of the 40nm 2D cell and about 30 times the 16nm 2D cell.

This is extremely important to realize especially since this physical area in 3D is unlikely to change over the proposed 3D technology generations to come.

When we project the effective electrical cell size onto the underlying silicon (taking into account the 2 electrical bits per physical cell), Samsung’s V-NAND comes out to about 840nm2 (being (155 X 260)/(2 X 24)). The relevant effective 2D cell size to compare with is the one at 16 nm, also with 2 electrical bits per cell. This is about 660nm2 (see Micron’s data below).

For comparison, Micron presented their 128Gbit 16nm planar 2D NAND with 2 electrical bits per cell in the same ISSCC session with the following attributes:

  1. Die dimensions are ~ 13.5mm by ~ 12.8mm.
  2. Array efficiency is ~ 75%.
  3. Physical cell size is ~ 1312nm2.
  4. Physical cell dimensions are ~ 32nm by ~ 41nm.

We can see that even with 24 stacked cell layers, this V-NAND starts out at a disadvantage compared to this aggressive 2D cell.

It is interesting to see how Samsung make virtue of necessity by claiming that the much larger effective channel area is good for threshold voltage distributions, but it is unlikely this is the reason they have such a large cell.

The narrative we are being encouraged to believe is of course that 2D is running out of steam, and that this vertical channel 3D NAND is the first of at least 5 generations that will snatch the baton and take us swiftly to 1 Tbit on a single chip.

Since Samsung have stated that they will remain at the 40nm node for all these generations, it appears that lateral shrinks will play only a minor role in achieving higher single chip capacities as was recently predicted.

Therefore, the main technique taking this to 1 Tbit will be more cell stacking with about the same cell size as given here unless the slit and hole taper angles force a progressively larger cell with all its additional disadvantages.

A 1 Tbit V-NAND chip will have vertical strings of 192 cells (8 times the 24 presented here). Remember worst case string current? Well, the experimentally measured value to expect for this is a few nanoAmps, which is orders of magnitude lower than what is sensed nowadays. This is a major hurdle in that race towards 1 Tbit.

In summary, this is an impressive achievement but not a realistic foundation for the future in my opinion.

It is interesting to consider that a simple litho-intensive layered 3D Flash approach that used cells at a node of 20nm could beat the capacity of this 24-layered vertical channel 3D NAND with only 2 device layers in the same chip area. This is only about 4 lithography steps more than this V-NAND. This kind of lithography adder is fairly standard when Flash memory is embedded in standard logic CMOS processes.

Wouldn’t it be nice to have such a laterally scalable litho-intensive technology that could provide a solid foundation for further single chip capacity increases towards 1 Tbit and beyond? Let’s also add the following to the wish list: endurance beyond a million cycles; no vanishing string currents; no new materials; no new “game-changing” manufacturing equipment; and all doable in existing logic fabs.

Wait until my next post to see how this can be done. ~ AJW

 

8 Comments

  1. Albert Bergemont - March 7, 2014, 1:17 pm Reply

    I do agree with the math at 40nm. Let’s do more math; it seems that at 40000nm2 cell size with 40nm geometries, VNAND , the physical cell size/layer is 25*40*40 = 25 (Lambda)2
    Let’s assume that scaling the physical dimensions is rough and the only way is by adding more layers; in another terms, let’s use a cell size of 25 (Lambda)2
    – At 20nm DRs, cell size will be ~ 10000nm2
    – At 10nm RDs, cell size will be ~ 2500nm2
    To make it easy , let’s assume same die sizes (133mm2) and AR (80%) at all geometries (decent assumptions).
    To achieve a 1024Gb at 20/10nm will require respectively 48/12 layers
    What’s wrong with that from a technical standpoint?

  2. Andy Walker - March 7, 2014, 4:53 pm Reply

    Thanks for the comment Albert. I suppose the key is to have a lateral shrink path to achieve 25F2 per layer with F at the values you mention. Looking at what parameters are in the cell pitches, it looks tough. Just taking the thickness of the gate dielectric memory stack, this by itself has remained at ~20nm for various reasons (their TANOS experiences). It just looks like lateral scalability is a roadblock and perhaps is the reason why Samsung mapped out their path to 1 Tbit by staying at the 40 nm node.

    Regards
    Andy

    • Albert Bergemont - April 16, 2014, 2:13 pm Reply

      Hi Andy
      Thanks for your comments; we both agree that 3d lateral scaling will be tough
      On another note , on MICRON 16nm MLC
      Die dimensions 173mm2
      Physical cell size 1312nm2
      Array efficiency cannot be 75%, but closer to 50%
      What do you think ? Am I right ?
      Best Regards
      Albert

  3. Andy Walker - April 16, 2014, 3:37 pm Reply

    Hi Albert,

    Thanks for your latest comments. I went back to my original notes where I calculated the array efficiency from their chip photograph in their ISSCC presentation and I still get ~75%. Now taking their cell sizes (also taken from their presentation), I get your number of ~50%. It looks like they are using quite a bit of area for extra cells.

    As to your comment that 3D lateral scaling will be tough, yes I agree for these kinds of architectures.

    Regards

    Andy

  4. Leo X - May 17, 2014, 9:03 pm Reply

    Hi Andy,

    Good article. I have a question about page size calculation. Assume BL pitch of 155nm, each plane is ~5.6mm in width, so we can fit ~35k BL’s – roughly 32k BL’s plus spares & ECC. So how do we get to 8kB page size (claimed in the paper) with only 32k BL / plane? something I missed? Don’t we need 64k BL’s to get 8kB page size?

    thanks,
    – Leo X

  5. Andrew Walker - May 18, 2014, 7:58 pm ReplyReport user

    Thanks for your compliment and question, Leo X. I think it works out if you take into account Samsung’s claim to have two electrical bits per physical cell.

    Regards

    Andy

  6. Chris - June 19, 2014, 11:17 am Reply

    Hi Andy!
    I just came across your article. Great job! I am not a designer but follow the semiconductor industry closely. The basic question is: is the die size of the 3D NAND or V-NAND larger the for 15/16nm 2D? I hope this will be an simple answer

  7. Andy Walker - June 19, 2014, 4:18 pm Reply

    Hi Chris,
    Thanks for your comments. The data from the ISSCC 2014 papers from Micron and Samsung was the following:
    – Micron 128Gbit 16nm 2bits/cell 2D NAND die size = 173.3 mm2
    – Samsung 128Gbit 24 layers 2bits/cell 3D V-NAND die size = 133 mm2.
    So a cursory comparison gives the V-NAND chip as smaller than the most advanced 2D at the same chip capacity (that I know of). However, the important things will be what is actually produced in fab where such numbers can change from their published values and what level of maturity each are at when being compared.
    Regards – Andy

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