Notes from GIT 2013

Notes from GIT 2013

The 3rd annual Global Interposer Technology Workshop (GIT 2013) was held at the Georgia Institute of Technology on November 18-20, 2013. Over 200 people from 11 countries attended this in-depth and lively discussion about interposers. Although many people think the conference is focused on glass (Glass Interposer Technology – another use of the GIT acronym) there was ample time given to silicon and organic alternatives. This was also the 20th anniversary of the Packaging Research Center at Georgia Tech. The initial vision for system scaling by system on package (SOP) was started in 1993 by Prof. Rao Tummala and appears to be going strong.

GIT 2013 Rau Tummala and Subu Iyer

Subu Iyer, IBM Fellow, presents Rao Tummala with a gift in honor of his 70th Birthday at the grand reception birthday
celebration at GIT 2013. It is an original special electrical probes invented by Rao in IBM.

The week started with the first GIT golf classic tournament on Sunday. Niine people enjoyed playing golf at Reynolds Plantation. The workshop started on Monday morning. The agenda included 14 keynote presentations along with 18 invited papers, a panel discussion, student poster session and Grand Reception celebrating Prof. Tummala’s 70th Birthday. Matt Nowak from Qualcomm was the co-chair for the program.

The program began with a keynote by Jeff Burns from IBM on the “design, technology and packaging for future high end systems – challenges and opportunities.” The focus here was on big data and high performance. A trend from CPU-centric to a data-centric model was proposed. Big data (meaning exabytes) is too costly to move. The analytics must be near the data to eliminate the transmission gap. It is interesting that we are going back to the mainframe concept and away from the Cloud. Disruptive technologies are needed to enable next generation subsystem scaling. The use of interposers and 3D are envisioned for these big data high end systems.

The next presentation was on the other side of the application space with Urmi Ray from Qualcomm talking about the “remote control for your life” or our “digital 6th sense”. Mobile is now an architectural approach and Urmi predicts a “mobile architecture tsunami” to occur with interposers playing a major role. The major challenge for mobile continues to be cost, however from a technical perspective it is thermal issues. Silicon, glass and organic are all contenders.

Bob Sankman from Intel presented “Organic Packaging: A User’s Perspective. Building on a long history of successful organic packaging, Intel appears to be pushing this technology as far as it will go. They believe that ongoing advances in organic materials and process will mitigate the need for alternative substrates.

Terry Bowen from TE Connectivity provided a new perspective on “Optical Interconnections in Interposers” where optical vias are made in glass interposers. A 2020 vision of an optically connected 3D supercomputer chip is being worked on collaboratively by IBM, Columbia University, Cornell and UCSB.

David McCann from Global Foundries discussed the market needs for interposers. The drivers for 2.5D are power and cost, where cost includes the design and scaling costs. Addressing the cost of scaling by partitioning the SoC will reduce the number of metal layers/device, allow the use of lower cost nodes and thereby lower the CAPEX for the foundry. These savings should offset the cost of the interposer. The lowest cost process flow needs to be developed and this means a focus on defect detection, which includes full test coverage at the wafer level, fine pitch probes, testing of interposers and via redundancy.

The 14 keynote speakers participated in the panel discussion. This provided lively dialogue from all perspectives (IDMs: Burns, Ray, Sankman, Bowe, McCann; OSATS: Hung, Huemoeller; Organic: Hu; Glass: Thomas, Imajyo, Wilkens; Consortia: Tummala, Lamy; Market Research: Garrou). The net of the discussions was that silicon interposers with fine-pitch wiring are ready and in low-volume production, however they do not meet the cost objectives for all applications. If fine-pitch RDL is required, then the same processes will be used on all substrates and the cost difference will be in the base interposer or core material. However for high-end applications, cost is last on the list of requirements (performance, reliability, thermal, time to market and then cost). Can silicon become cheap enough for a particular application? Obviously Xilinx believes it is. Glass has performance benefits but is lacking a supply chain. The LCD industry is set up for handling large glass panels and doing wiring, however it is not set up for thick plated copper. Organic interposers continue to make technical progress in line dimensions but the question that still remains is the ability to do fine-pitch wiring. Possibly a hybrid approach is possible. In the end the volume will drive the cost and not the technology.

Phil Garrou presented a market trend update.  Xilinx, TSMC and Micron made announcements in 2010-2011. We are still waiting for further adoption (Qualcomm, Apple and Sony) however these have been delayed by the price point problem. HMC appears to be on track for 2014-15 production. The IP landscape has been active with 616 patents issued and 713 pending in 2.5D/3D technologies. The major players (Micron, IBM, Samsung and TSMC) have significant patent positions.

All three glass companies (Asahi, Corning and Schott) showed great progress in making vias in glass panels, however the most entertaining of the presentations was by Windsor Thomas from Corning on the “Manufacturing Readiness of Glass Interposers”. Corning says they have the 3Cs required: Capability, Cost and Capacity and have gone from the lab to the “fabette”. A Gen 2 glass panel with vias and sputtered metal was available for show and tell.

GIT 2013

Speed in drilling the vias is not the most important parameter. Speed is nothing without control and the ability to form a proper shaped via without damaging the glass. For ease of handling and processing the glass panels can be temporarily bonded to a glass carrier.

There were many more presentations and I could go on for several pages describing all of the progress made in via formation, metallization, mechanical and thermal design along with applications for interposers. It should be interesting to see what the next year brings along with the 4th annual workshop on interposers. ~ LM

3 Comments

  1. Dr. Dev Gupta - November 26, 2013, 11:36 am Reply

    Laura, thx for your nice summary. Could you expand some more on what Bob Sankman from Intel had to say about the prospects of organic substrates for interposers ?

    Given interconnect density ( speed, power ) vs cost trade – offs, organic interposers actually have a better chance of wide adoption than Si or glass, specially when populated on both sides ( minimizes RDL on dice or horizontal traces on the Interposer – giving better speed & power at lower cost ).

    • Laura Mauer - November 26, 2013, 4:04 pm Reply

      The presentation provided more of a historical perspective on the use of organic substrates from the Pentium II in 1998 through the Core i7 this year. Many changes have occurred in the die to package interconnects as the groundrules shrink. Current organic substrates do not support the ultra-high bandwidth on-package interconnect requirements. Material selection and manufacturing process optimization will be needed.

      • Dr. Dev Gupta - November 28, 2013, 8:02 am Reply

        Thx. and Happy Thanksgiving

        Would still appreciate more on Bob’s paper especially if he had anything on the future prospects for shrinking the L/S/ via diameter of Organic substr. and improving their planarity and whats being done now to make it happen.

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